The RNS-TPU™ is the world’s first tensor processing unit built entirely on residue number system (RNS) arithmetic. Unlike traditional binary designs, the RNS-TPU performs matrix and vector multiplications using carry-free, modular operations that enable ultra-fast, parallel computation with inherently low switching activity—yielding dramatically lower power consumption and thermal load. This architecture achieves exceptional numerical precision through scalable digit widths, making it ideal for high-accuracy AI workloads.
Designed for high-performance AI and scientific applications, the RNS-TPU™ excels in massive matrix multiplication and summation tasks common to deep learning, search, simulation, and financial modeling. Its low-entropy arithmetic model preserves information density across computation stages, enabling more stable learning dynamics and reducing energy waste per inference or training step. Available as Verilog IP, RNS-TPU™ integrates seamlessly into FPGA and ASIC workflows, offering a drop-in solution for next-generation, precision-driven AI accelerators.
The EC-TPU™ is the world’s first error-correcting tensor processor built on modular RNS arithmetic. Leveraging the carry-free, high-precision architecture of the RNS-TPU™, the EC-TPU™ adds a forward error correction layer capable of detecting and correcting faults in vector and matrix computations—without requiring full circuit triplication. This innovative approach achieves robust arithmetic integrity with minimal overhead, ensuring reliable performance even in environments prone to soft errors, radiation effects, or long-duration operation.
Designed for demanding applications where reliability cannot be compromised, the EC-TPU™ targets advanced AI workloads, aerospace and defense systems, financial engines, and scientific computing platforms. Its seamless correction of arithmetic errors enables sustained accuracy in deep learning, inferencing, and simulation pipelines—now and into the future. Delivered as Verilog IP, the EC-TPU™ is ready for FPGA or ASIC integration, offering unmatched error resilience and efficiency for next-generation computing.
The Mod-9™ ALU is the world’s first general-purpose arithmetic processor built entirely on residue number system (RNS) principles. Delivered as a soft co-processor for Intel’s Nios® II CPU and compatible with the Terasic DE2-115 development board, Mod-9™ brings modular computation into a standard processor environment for the first time. This revolutionary ALU executes all arithmetic using 18 carry-free, 9-bit residue digits—enabling fast, parallel, and precise operations on data widths far beyond traditional limits.
Designed for engineers, researchers, and educators, the Mod-9™ offers hands-on access to the future of numerical computing. Its native support for fractional RNS formats allows exact representation of complex rational values that binary systems cannot express. With seamless binary and floating-point conversion instructions, Mod-9™ opens new doors for algorithm design in scientific simulation, AI prototyping, fractal generation, and high-precision computing—all within the professional, Eclipse-based Intel development flow.
RNS-APAL™ is the world’s first C++ library for arbitrary precision arithmetic built entirely on the Residue Number System (RNS). Unlike traditional fixed-radix libraries that rely on carry propagation, RNS-APAL™ executes all computations in a fully modular, carry-free domain. It includes complete support for high-precision integer and fractional arithmetic, with routines for modular division, scaling, and iteration—making it an essential tool for demonstrating and exploring the power of modular computation.
Designed for research, education, and hardware co-design, RNS-APAL™ is ideal for developing and validating modular algorithms, generating test vectors, and building test benches for RNS-based hardware. The library is freely available to students and academic institutions for non-commercial use. For commercial licensing or integration into hardware development workflows, including AI accelerators and cryptographic engines, please contact MaiTRIX for licensing options.
MaitrixLib™ is our powerful collection of modular computation Verilog IP suitable for use with ASIC and FPGA designs. Several libraries are offered, including a powerful pipe-lined data flow IP library, a scalar, multi-cycle IP library, and a crypto library (CryptoLib™ coming soon). MaitrixLib™ also comes with a complete set of tools allowing easy generation of test vectors and hex files LUT file generator to support customized word-lengths and digit modulus. Coming Soon!