Mod-9 ALU

The Mod-9 is the world’s first and only residue based, general purpose arithmetic processor! The Mod-9 is a major break-through in computer science and engineering. Experiment with the Mod-9 by writing programs which execute on MaiTRIX’s modular ALU using state of the art development tools! See the power of an ALU comprised of 18 residue digits, each being only 9-bits wide!

The Mod-9 is currently available as a soft FPGA co-processor attached to the Intel NIOS-II soft processor and may be used with the DE2-115 development board from Terasic.


The RNS-TPU is the world’s first residue-based tensor product unit, initially released as a matrix multiplier, and is an advanced FPGA based processor line compatible with Intel’s Avalon interface. The RNS-TPU offers significant performance advantages, including high efficiency of product summations, high-speed operation, and very high accuracy.

The RNS-TPU family of processors target high-end accelerator applications for Artificial Intelligence (AI), web search and other high-end computation involving massive product summation. RNS-TPU is available as Verilog IP suitable for FPGA or ASIC implementation.


The TPU-ec is the world’s first error correcting tensor processor and matrix multiplier unit. The TPU-ec exploits the power of the RNS-TPU but adds a powerful error correcting unit capable of correcting vector and matrix arithmetic! The TPU-ec requires much less circuit resources over old-fashioned triplicated circuits while providing an unprecedented level of error detection and correction of high precision arithmetic!

The TPU-ec family of processors target high-end, mission critical applications which require high reliability while also providing unprecedented efficiencies for processing AI or other numerical applications involving massive product summations and matrix multiplication. TPU-ec is available as Verilog IP suitable for FPGA or ASIC implementation.


RNS-APAL is our residue number arbitrary precision C++ numeric simulation library. RNS-APAL can be used to demonstrate how modular computation works by showing source code for fractional methods and integer methods of modular computation. RNS-APAL includes long division routines, scaling routines and all fractional libraries for basic arithmetic operations. RNS-APAL is a mandatory tool for research and development into modular computation, and to develop sophisticated modular computation applications, including the generation of check vectors and test benches for the development of modular computation hardware.

RNS-APAL is available for free to academics and students for educational and research purposes only. For commercial applications, such as developing test benches and test vectors for actual hardware development, contact MaiTRIX for a suitable license.


MaitrixLib is our powerful collection of modular computation Verilog IP suitable for use with ASIC and FPGA designs. Several libraries are offered, including a powerful pipe-lined data flow IP library, a scalar, multi-cycle IP library, and a crypto library (CryptoLib coming soon). MaitrixLib also comes with a complete set of tools allowing easy generation of test vectors and hex files LUT file generator to support customized word-lengths and digit modulus.