Error Correcting Tensor Processor Unit (EC-TPU™)
MaiTRIX’s forward error-correcting technology is combined with its RNS-TPU™ to provide the world’s first error correcting matrix arithmetic!
Extreme Reliability TPU
The EC-TPU™ is extremely resilient to transient bit errors from sources as diverse as over-clocking and over-heating, and from single and multiple event error sources in outer space, such as gamma rays and neutron particle strikes. No other processor architecture comes close. Prior art technology, such as binary matrix processors configured in a triplicate voting configuration, cannot correct more simultaneous errors than DSR’s new EC-TPU™ error correcting TPU technology!
For FPGA based designs, our EC-TPU™ can operate and deliver continuously corrected matrix arithmetic during critical single event upsets (SEU) and multiple event upsets (MEU), even when these events are located in the configuration RAM (CRAM) cells of FPGA devices. When CRAM is corrupted, the circuit configuration of the ALU actually changes. For example, one entire digit circuit of the EC-TPU™ matrix multiplier may be rendered faulty when a CRAM cell changes, yet the matrix arithmetic will not be affected. Un-like the case of triplicate redundancy, with Maitrix technology the exact point of failure can be instantly located, and the local CRAM configuration can be repaired.
MaiTRIX’s error correcting technology requires a 50% increase of total arithmetic circuitry and corrects multiple, simultaneous errors versus triplication schemes which require a 200% increase in arithmetic circuitry yet cannot correct multiple, simultaneous errors.
Extreme Reliability Meets Extreme Efficiency
When MaiTRIX’s new error correcting technology is combined with its RNS-TPU™ technology, we call it extreme reliability meets extreme efficiency! … a perfect combination for advanced space-based AI applications!
For off the shelf solutions, our EC-TPU™ IP cores are tailored to run on Arria 10, Stratix 10, and Agilex FPGA devices from Intel. Demonstration cores are available for popular development boards from Intel and Terasic. MaiTRIX IP supports a wide range of Intel based accelerator cards to support applications that demand high-performance, high precision, and high efficiency combined with very high reliability.
Contact MaiTRIX for more information.
See our Live Error Correcting Arithmetic Demonstration:
Preliminary Specifications for Arria 10 based EC-TPU 1.0
Now Available courtesy of Maitrix:
- RNS Error Correcting Arithmetic Demo Code !
- This demonstration is based on RNS-APAL and includes code that demonstrates error correction of signed arithmetic.
- DOWNLOAD USER License is Creative Commons License: CC BY-NC-SA
- FPGA based Error Correcting Arithmetic Demo!
- This demonstration is a fully functional FPGA demonstration of a high-speed RNS product accumulator with error correction.
- Demonstration includes high speed conversion modules operating in a fundamental RNS fixed-point format.
- Complete Verilog source code version included.
- Intended for research purposes only.
- DOWNLOAD USER License is Creative Commons License: CC BY-NC-ND
* EC-TPU™ is a trademark of MaiTRIX, Llc.
Our source code library comprises fundamental research and is published compliant to Section §734.7, §734.8 & §734.10 of the U.S. EAR export rules and is therefore available for public dissemination. However, the download of our source technology does not provide a commercial license, please contact MaiTRIX for a license allowing commercial use. Commercial use of Maitrix technology includes the use of the source technology to develop RNS based ALU and CPU technology.