Error Correcting Tensor Processor Unit (TPU-ec)

DSR’s breakthrough error-correcting technology is combined with its RNS-TPU to provide for an un-parallel level of error detection and correction of matrix arithmetic!

Extreme Reliability TPU

The TPU-ec is extremely resilient to transient bit errors from sources as diverse as over-clocking and over-heating, and from single and multiple event error sources in outer space, such as gamma rays and neutron particle strikes. No other processor design even comes close. Prior art technology, such as binary matrix processors configured in a triplication or quadruplication voting configuration, cannot correct more simultaneous errors than DSR’s new TPU-ec error correcting technology!

DSR’s error correcting technology requires a 50% increase of total arithmetic circuitry and corrects multiple, simultaneous errors versus triplication schemes which require a 200% increase in arithmetic circuitry yet cannot correct multiple, simultaneous errors.

Extreme Reliability Meets Extreme Efficiency

When DSR’s new error correcting technology is combined with its RNS-TPU technology, we call it extreme reliability meets extreme efficiency! … a perfect combination for advanced space-based AI applications!

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Preliminary Specifications for Arria 10 based RNS TPU 1.0

Now Available courtesy of Maitrix !

RNS Error Correcting Arithmetic Demonstration Code !

*TPU-ec and related error correcting technology are inventions of MaiTRIX Inc and are patent pending in the US and abroad;

* TPU-ec is a trademark of MaiTRIX, Inc