• October 23, 2022:  MaiTRIX to demonstrate its new RNS TPU technology.  Maitrix unveils a first prototype of its RNS TPU matrix multiplier processor.  Maitrix is actively developing TPU technology using its non-binary, modular computation number system.  Today, it has announced it will demonstrate the RNS TPU technology at the upcoming SC22 show, Dallas TX, November 14-17, booth #447.  See our whitepaper.  
  • April 6, 2022:  MaiTRIX embarks on an advanced AI processor design using modular computation.  MaiTRIX has revealed its intent to enter the AI processor technology space.  MaiTRIX states: “MaiTRIX’s modular computation technology is now primed to be deployed into an AI processor capable of higher levels of efficiency, and higher levels of precision.  The race to a better AI processor is complex and costly, however, MaiTRIX’s approach does not rely on risky incremental technology advances.  Instead, MaiTRIX technology can be applied to the best-in-class architectures now being developed and proven by others.  Our aim is to combine the best of modular computation to the best-in-class AI processor architecture to achieve leapfrog advancements never before contemplated.”  MaiTRIX, LLC is an AI processor and IP technology company.
  • December 27, 2021:  Maitrix selects Intel as preferred FPGA partner.  Maitrix has announced it has selected Intel FPGAs as a preferred re-programmable device for implementation of its core IP.  We have carefully evaluated all of the competition and have concluded Intel’s FPGA technology favors our mission to advance modular computation technology.  Of course, most FPGA devices can be used to host Maitrix IP, but we have selected Intel FPGAs to target our carefully tuned matrix multiplier IP.  Maitrix will also use Intel FPGA devices in all public exhibitions and evaluation boards in 2022.
  • April 27, 2021:  USPTO grants key patent for MaiTRIX’s error correcting arithmetic technology.  Maitrix has pioneered a new form of error correcting arithmetic that vastly outperforms prior art triple modular redundancy (TMR) and other similar techniques.  Instead, Maitrix’s new technology provides high-speed error detection and correction of arithmetic within a decoupled arithmetic pipeline.  This results in continuous error detection and correction of arithmetic on a massive scale.  “Modular computation on its own demonstrates significant resilience to errors, even when over-clocked.  However, combining modular computation with our new error correcting technology provides for a new level of error resiliency never seen before.  We’ve been able to operate our modular FPGA based circuits well beyond the maximum clock rates of those devices.  Binary circuits can’t come close.”  Maitrix’s error correction technology can be integrated into its RNS-TPU and MOD-9 modular computation processors.  
  • August 1, 2019USPTO issues patent for MaiTRIX’s TPU technology. MaTRIX has pioneered a new architecture for matrix multiplication which partitions each digit of the number format into it’s own matrix multiplier.  This results in very high speed operation for matrix multiplication, and provides for a linearly scalable solution versus arithmetic precision.  “We are pleased the patent office has recognized our break-through methods for processing product summations using our advanced modular multiplier-accumulator architecture. Product summation is the core operation for just about all AI algorithms in use today, and our technology is proving to have superior performance in nearly all metrics applied so far, including efficiency, speed, accuracy, and error immunity.”
  • April 6, 2018 – MaiTRIX reports significant breakthroughs with TPU development. MaiTRIX is announcing it has made significant breakthroughs in Modular Computation which have significant impact for MaiTRIX’s new TPU matrix multiplier and other MaiTRIX technologies. “The most I can say at this time is we’ve significantly increased our understanding of fixed-point arithmetic. Let me add these improvements only strengthen and bolster our position modular computation will become the preferred method of cloud-based neural network processing. We’ve been off the fence for a long time here at MaiTRIX, but advancements like this tear the fence down”.
  • Jan 1, 2018 – MaiTRIX posts informative presentation describing basic RNS ALU design. Computer systems which employ the newly emerging science of Modular Computation are unique and have surprisingly different computer architecture than conventional binary systems. As always, it helps to start with some simple examples, and clear explanations of the some of the problems solved using IP developed by MaiTRIX. Download it at: RNS_ALU_Design.
  • Oct 22, 2017 – MaiTRIX posts upgrade to its RNS-APAL software library. The upgrade includes a few fixes and is accompanied with a revised RNS-APAL User Guide and Tutorial Guide V1.05. See our downloads page. MaiTRIX is now calling general purpose RNS arithmetic “modular computation“.
  • Oct 2, 2017 – Canadian patent office issues patents to MaiTRIX. MaiTRIX is granted key Canadian patents in area of residue number processing and residue number computer systems.
  • Sept 25, 2017 – USPTO grants patent for improved multiplier and converter. “Our licensed patent portfolio has grown again by the addition of a key patent for an improved RNS multiplier, which provides a means to process fractional quantities using completely modular arithmetic without carry. Our combined portfolio of IP continues to grow as MaiTRIX continues its push to exploit this re-awakened technology. Recently, we’ve taken what we know and we’re applying this to a new class of computing machine which targets AI and deep learning applications. We’re still in the infancy stage of our hardware design, but initial results are quite impressive.” MaiTRIX is engaged in design, development and licensing of residue-based processor and other unique digital technologies.
  • July 19, 2016 – USPTO grants key patent underlying residue-based product summation technology. “Once again, we are excited the US patent office has recognized our advanced residue-based product summation methods and technology. Because emerging technologies such as artificial intelligence rely on vast amounts of product summations, MaiTRIX is confident that residue-based systems will emerge as a preferred methodology as it provides the fastest rates, lowest power consumption, highest accuracy and built-in redundancy. In fact, product summation is the new motivation behind the pursuit of residue-based processing systems.” MaiTRIX is engaged in design, development and licensing of residue-based processors and other unique digital technologies.
  • April 7, 2015 – USPTO grants key patent underlying advanced residue-based processor technology. “We are excited the US patent office has recognized our technology by granting a key patent. Through a unique partnership, MaiTRIX acquires exclusive rights to sub-license the new technology for CPU and other arithmetic processing applications. This is an exciting time for MaiTRIX as we expect many more advancements in the months ahead”. MaiTRIX is engaged in design, development and licensing of residue-based processors and other unique digital technologies.
  • November 15, 2014 – MaiTRIX unveils Mod-9 ALU performing general purpose calculations. “We are excited to unveil our Mod-9 ALU, the first residue number-based processor capable of general purpose calculations. The Mod-9 ALU is easily programmed using the NIOS-II IDE environment from Altera, and in our first demonstration we show the ability of the Mod-9 processor to accurately depict Mandelbrot fractal images. The accuracy of the iterative calculations is stunning, and we are excited to see the processor concretely demonstrated”.


  • IEEE CCWC 2020 – 10th Annual Computing and Communication Workshop and Conference.  Las Vegas, Nevada. 
  • SC19 November 18-21, Denver, Colorado
    • The International Conference for High Performance Computing, Networking, Storage, and Analysis.   MaiTRIX invites you to stop by our booth to see our error correcting arithmetic demonstration!
  • ISCAS 2018, May 30, Florence Italy.
    • MaiTRIX invites you to ISCAS 2018, the premier IEEE symposium for the advancement of circuits and system design. MaiTRIX will provide a short presentation of its RNS TPU. This presentation will provide an overview of fractional multiplication in the modular domain, the development of a high-speed modular accumulator, and extrapolated performance metrics of the RNS TPU.