Error Correcting Tensor Processor Unit (EC-TPU™)
When AI Reliability Matters Most
MaiTRIX’s EC-TPU™ is the world’s first error-correcting matrix arithmetic processor, combining our advanced Residue Number System architecture (RNS-TPU™) with breakthrough Forward Error Correction of Arithmetic (FECA) technology. Unlike traditional approaches that detect faults after the fact, FECA enables real-time correction of arithmetic results — even during active computation. Designed to survive both transient and permanent faults, the EC-TPU redefines what’s possible in high-reliability numerical processing.
Architected for Extreme Reliability
The EC-TPU™ provides a resilient, fault-tolerant compute core for AI, scientific, and edge workloads operating in error-prone environments. Unlike traditional voting-based redundancy schemes—which require triplicate hardware and still struggle with simultaneous faults—the EC-TPU detects and corrects multiple concurrent errors of arithmetic using only a 50% overhead. That’s 4× the resilience per unit of silicon compared to TMR (Triple Modular Redundancy).
It corrects TPU operations from:
• Transient logic faults from overclocking or thermal stress
• Cosmic radiation events like gamma rays, heavy ions, and neutron strikes
• Single and multi-bit upsets (SEU/MEU) in FPGA configuration RAM (CRAM)
Even when an entire digit pipeline becomes faulty due to a CRAM event, EC-TPU matrix results remain correct—and the exact fault location is identified for live reconfiguration.
RNS-Based Forward Error Correction of Arithmetic: A New Standard
At the heart of EC-TPU lies the Modular Computation Engine, built from digit-level matrix multipliers using RNS arithmetic. Each digit operates independently with no carry propagation, which:
• Prevents fault propagation
• Enables localized error detection and correction
• Supports redundant moduli for FEC of arithmetic
• Maintains full matrix throughput—corrects faults on the fly
This architecture achieves forward error correction directly in arithmetic space, rather than relying on data duplication or checkpoints. It is the first known processor architecture that continuously self-corrects during dot-product accumulation.
Targeted Applications: Today and Tomorrow
Today’s Needs
• Space AI systems – satellite swarm coordination, deep-space navigation, edge inference
• Autonomous vehicles – hardened safety processors for high-confidence decisions
• Financial trading – glitch-immune calculations in ultra-low-latency environments
• Quantum simulation – carry-free arithmetic for long-term fidelity in high-precision math
Tomorrow’s Vision
• Self-healing neural networks trained with fault-tolerant hardware
• Defense systems operating in degraded or contested electronic environments
• Exascale computing with fine-grained fault containment
• Deep Space Artificially Intelligent probes
Live Demonstration:
Live Demonstration: Resilient Modular Arithmetic in Action
This video demonstrates the core advantage of MaiTRIX’s forward error-correcting technology: the ability to perform high-speed product summation — using signed 32.32 fixed-point RNS arithmetic — even while aggressively overclocking the hardware. The multiply-accumulate unit is intentionally pushed beyond safe operating limits, yet accurate results are still recovered through digit-level error correction.
In addition to overclocking-induced faults, background errors are continuously injected by a dedicated circuit to simulate high-rate random failures. These artificial errors are distributed across all RNS digits and are designed to occasionally cause multiple-digit corruption within a single result — a condition that exceeds the system’s single-digit correction capability. While these multi-digit faults are detected and flagged, they are not corrected in this demonstration.
As the clock frequency exceeds 400 MHz on an Arria-10 FPGA device, the system dynamically identifies and corrects single-digit errors in the dot products. Corrected values appear in yellow, while uncorrectable multi-digit errors are clearly flagged in red. This provides transparent, real-time feedback on the health of every matrix result.
What makes this technology powerful is that error correction is done in arithmetic space — not just as a post-check — allowing deep pipelines to recover from hardware faults without halting execution. This makes the EC-TPU uniquely suited for mission-critical and radiation-prone environments, or any application pushing the limits of performance and reliability.
Deployable Now – Contact us with your requirements
EC-TPU™ IP cores are optimized for Intel’s:
• Arria-10
• Stratix-10
• Agilex FPGA families
Turnkey demos are available on development platforms from Intel and Terasic. Our IP supports many Intel accelerator cards, ready to drop into AI pipelines or custom RTL workflows.
Subtitle for This Block
Title for This Block
Text for This Block
* EC-TPU™ is a trademark of MaiTRIX, LLC.
Our source code library comprises fundamental research and is published compliant to Section §734.7, §734.8 & §734.10 of the U.S. EAR export rules and is therefore available for public dissemination. However, the download of our source technology does not provide a commercial license, please contact MaiTRIX for a license allowing commercial use. Commercial use of Maitrix technology includes the use of the source technology to develop RNS based ALU and CPU technology.