[fusion_builder_container hundred_percent=”no” equal_height_columns=”no” menu_anchor=”” hide_on_mobile=”small-visibility,medium-visibility,large-visibility” class=”” id=”” background_color=”” background_image=”” background_position=”center center” background_repeat=”no-repeat” fade=”no” background_parallax=”none” parallax_speed=”0.3″ video_mp4=”” video_webm=”” video_ogv=”” video_url=”” video_aspect_ratio=”16:9″ video_loop=”yes” video_mute=”yes” overlay_color=”” video_preview_image=”” border_size=”” border_color=”” border_style=”solid” padding_top=”” padding_bottom=”” padding_left=”” padding_right=””][fusion_builder_row][fusion_builder_column type=”1_1″ type=”1_1″ background_position=”left top” background_color=”” border_size=”” border_color=”” border_style=”solid” border_position=”all” spacing=”yes” background_image=”” background_repeat=”no-repeat” padding_top=”” padding_right=”” padding_bottom=”” padding_left=”” margin_top=”0px” margin_bottom=”0px” class=”” id=”” animation_type=”” animation_speed=”0.3″ animation_direction=”left” hide_on_mobile=”small-visibility,medium-visibility,large-visibility” center_content=”no” last=”true” min_height=”” hover_type=”none” link=”” first=”true”][fusion_text]
Maitrix has announced an error correcting TPU processor designated TPU-EC. The TPU-EC is a breakthrough in ALU design since it allows continuous error detection and correction of matrix arithmetic. The additional resources required by DSR’s error correcting technology is as low as 25% overhead compared to the 200% overhead of traditional triplication schemes. Moreover, the error correction system of the TPU-ec can correct multiple errors in a single matrix operation without affecting the speed of processing or accuracy of results delivered by the TPU. The TPU-EC is available as an FPGA library or IP suitable for ASIC and custom IC. FPGA based performance specifications for the TPU-ec are expected 3rd quarter 2019.
[/fusion_text][/fusion_builder_column][/fusion_builder_row][/fusion_builder_container]