Maitrix has announced an error correcting TPU processor designated TPU-EC. The TPU-EC is a breakthrough in ALU design since it allows continuous error detection and correction of matrix arithmetic. The additional resources required by DSR’s error correcting technology is as low as 25% overhead compared to the 200% overhead of traditional triplication schemes. Moreover, the error correction system of the TPU-ec can correct multiple errors in a single matrix operation without affecting the speed of processing or accuracy of results delivered by the TPU. The TPU-EC is available as an FPGA library or IP suitable for ASIC and custom IC. FPGA based performance specifications for the TPU-ec are expected 3rd quarter 2019.